1. Field of the Invention
The present invention relates to a solid state image pickup device that performs analog-to-digital (A/D) conversion converting an analog voltage signal output from a pixel into binary digital data.
Priority is claimed on Japanese Patent Application No. 2011-003983, filed Jan. 12, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In recent years, image pickup devices, such as digital cameras and digital video cameras, that acquire an imaged image as digital data using a solid state image pickup device (hereinafter referred to as an “image sensor”), and store or edit the image have been in widespread use. As an image sensor used in the image pickup device, charge coupled device (CCD) image sensors have been most commonly and widely used. However, in recent years, there have been demands for a reduction in the size of the image sensor and low power consumption, and thus complementary metal oxide semiconductor (CMOS) image sensors have attracted attention and become widespread. With the size reduction and low power consumption of the image pickup device, a compact A/D converter of low power consumption has been suggested as an A/D converter used in the image sensor (for example, see Japanese Patent No. 3064644).
The A/D converter includes a pulse delay unit configured by a plurality of inverting circuits (delay elements) which are connected in a ring form. An analog input signal, which is an input signal, is applied to each inverting circuit (a delay element) as a power voltage. Using a phenomenon in which a delay time of a pulse in an inverting circuit (delay element) changes depending on the power voltage, the number of times that the pulse has circulated in the pulse delay unit within a time period for performing A/D conversion (hereinafter referred to as a “sampling time period”) is counted. The count value is used as a upper bit, and a value obtained by encoding a position of the pulse inside the pulse delay unit is used as a lower bit. A/D conversion of the analog input signal is performed by synthesizing output values of the upper bit and the lower bit.
Further, a pulse phase difference encoding circuit using the above described pulse delay unit that causes a first pulse input at an arbitrary timing to circulate in the pulse delay unit, counts the circulation number, specifies a circulation position of the first pulse at an input timing of a second pulse input with an arbitrary phase difference, and detects a phase difference between the two pulses using the specified position and a count number of the circulation number of the first pulse has been suggested (for example, see Japanese Patent No. 2868266 and Japanese Patent No. 3455982).
In particular, in Japanese Patent No. 2868266, two counter units for counting a circulation number of a pulse are provided. The two counter units perform a count operation at different timings, and only an output value of the counter unit having a stabilized output value when the count operation is finished is used. Thus, the phase difference can be accurately detected by constantly using the counter value of a stabilized state.
In Japanese Patent No. 3455982, one counter unit for counting a circulation number of a pulse and two latch units for latching an output value of the counter unit are provided. By operating the two latch units at different timings, it is possible to constantly use the count value of a stabilized state, and thus the same effect as in Japanese Patent No. 2868266 is obtained. When the technique disclosed in Japanese Patent No. 2868266 and Japanese Patent No. 3455982 is applied to the technique disclosed in Japanese Patent No. 3064644, an improvement in the conversion accuracy of the A/D converter can be similarly secured.
However, when the above described A/D converter is employed in a CMOS image sensor (a CMOS image sensor of a column analog-to-digital converter (ADC) type) which is an example of a CMOS image sensor and includes an A/D converter arranged for each pixel column or for a plurality of pixel columns, the following problems occur. The problems will be described below.
FIG. 23 is a block diagram illustrating an example of a CMOS image sensor using the above described A/D converter. The CMOS image sensor illustrated in FIG. 23 includes a pixel unit 001, a vertical scanning unit 003, an analog signal processing unit 004, an A/D converter 005, a memory unit 006, an output unit 007, a horizontal scanning unit 008, and a control unit 009.
The pixel unit 001 includes a plurality of pixels 002 arranged in the form of a matrix. The pixel 002 generates a pixel signal based on light incident thereto. Each pixel 002 is connected to a pixel signal output line (a vertical signal line) arranged for each pixel column. The pixel signal generated from each pixel 002 is output to the corresponding pixel signal output line.
The vertical scanning unit 003 outputs various kinds of control signals to the pixel 002 and controls an exposure operation or a signal read operation of the pixel 002. The analog signal processing unit 004 performs a process such as a sample-and-hold operation on an analog pixel signal output from the pixel 002. The A/D converter 005 A/D-converts the analog pixel signal processed by the analog signal processing unit 004, and generates digital data. The memory unit 006 stores the digital data which is the A/D conversion result. The output unit 007 outputs the digital data stored in the memory unit 006 to a processing circuit of a subsequent stage. The horizontal scanning unit 008 controls reading of the digital data from the memory unit 006. The control unit 009 outputs control signals 010 and 011 to the A/D converter 005, and thus controls an operation of the A/D converter 005.
In the CMOS image sensor of this example, the A/D converter 005, the analog signal processing unit 004, and the memory unit 006 are provided for each pixel column. In each column, the analog signals from the pixels 002 are output to the analog signal processing unit 004. The analog signal processing unit 004 processes the analog signals, and outputs the processed analog signals to the A/D converter 005. The A/D converter 005 is controlled by the control unit 009, A/D-converts the input signal while the control signals 010 and 011 from the control unit 009 have a high (H) level, and outputs the A/D-converted digital data to the memory unit 006. Operation start and operation stop of a counter unit 0052 constituting the A/D converter 005 are controlled by the control signal 010, and operation start and operation stop of a pulse delay unit/latch unit 0051 constituting the A/D converter 005 are controlled by the control signals 010 and 011.
In the A/D converter of the CMOS image sensor having the above described configuration, the pulse delay unit/latch unit 0051 and the counter unit 0052 are arranged in a line in a vertical direction as illustrated in FIG. 23. For this reason, a delay corresponding to a difference in the line length of the control signal 010 occurs. Due to the delay, a timing at which the control signal 010 reaches the pulse delay unit/latch unit 0051 is different from a timing at which the control signal 010 reaches the counter unit 0052 (specifically, a timing at which the control signal 010 reaches the counter unit 0052 is delayed), so that an error may occur in the A/D conversion result.
This problem will be described with reference to FIG. 24. FIG. 24 is a timing chart for explaining the problem of the related art. In FIG. 23, the line of the control signal 010 to the counter unit 0052 is longer than the line of the control signal 010 to the pulse delay unit/latch unit 0051, and thus a time difference of Δt occurs in the control signal 010 between a point A and a point B. That is, the control signal 010 reaches the counter unit 0052 at a timing which is delayed by Δt from a timing at which the control signal 010 reaches the pulse delay unit/latch unit 0051.
As illustrated in FIG. 24, when the counter unit 0052 counts the output signal from the pulse delay unit during the delay Δt, an output value (11 in FIG. 24) of the counter unit 0052 is one count larger than a normal output value (10 in FIG. 24). The error of one count in the counter unit 0052 results in a deviation corresponding to an output bit of a lower bit of digital data from the point of view of an output result of the A/D converter in which an output value of the counter unit 0052 (which is the upper bit of the digital data) is synthesized with an encoding result of a pulse position of the pulse delay unit/latch unit 0051 (which is the lower bit of the digital data).
In FIGS. 23 and 24, the counter unit 0052 performs erroneous count by +1 due to the delay of the control signal 010, and the error occurs in the A/D conversion result. However, depending on the line layout of the control signal 010, the delay of the control signal 010 may occur in the pulse delay unit/latch unit 0051, and the counter unit 0052 may perform erroneous count (minus one different), leading to an error in the A/D conversion result.
When the delay of the control signal 010 occurs in the pulse delay unit/latch unit 0051, the error in the A/D conversion result can be prevented by applying the technique disclosed in Japanese Patent No. 2868266 to the technique disclosed in Japanese Patent No. 3064644. However, when the delay of the control signal 010 occurs in the counter unit 0052, the error occurs in the A/D conversion result as described above.
Further, even when there is no difference (or a small difference) in the line length of the signal line, a random signal deviation may occur due to overlapping of a clock signal from another signal line. In this case, in the example of the delay of the control signal 010 between the points A and B of FIG. 23, even though the length from a reference point to the point A is the same as the length from the reference point to the point B, when the control signal 010 at the point A is delayed compared to the control signal 010 at the point B due to influence of the clock signal overlapping midstream, the control signal 010 at the point B may be delayed compared to the control signal 010 at the point A.
In addition, in the pulse phase difference encoding circuit disclosed in Japanese Patent No. 2868266, the two count units are provided. Thus, in the CMOS image sensor of the column ADC type of the above described example, when the A/D converter is arranged for each pixel column or for a plurality of pixel columns, the size of the A/D converter increases, leading to an increase in the chip size.